Optimized gate driver for low voltage power loss protection system

ABSTRACT

An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. patent application Ser. No. 15/633,662, filed Jun. 26, 2017, which claims the benefit under 35 U.S.C. § 119 of provisional application Ser. No. 62/354,740, entitled “Optimized Gate Driver For Low Voltage Power Loss Protection System”, filed Jun. 25, 2016, the disclosures of which are hereby incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates generally power loss protection circuits and to related methods.

BACKGROUND INFORMATION

Capacitors and/or batteries are used to store energy in power loss protection systems. FIG. 1 (Prior Art) illustrates one example of a power loss protection system 100 for powering a device. The power loss protection system 100 involves a so-called “eFuse” 101, a switch component 102, enable trip point resistors 103 and 104, a boost converter circuit 105, a bank of capacitors and/or batteries 106, and a voltage regulator 107. This circuitry is soldered onto a printed circuit board. During normal operation of the power loss protection system, when the system is powering the device, the boost converter 105 receives some of the power from the eFuse output and uses that to charge the capacitors and/or batteries 106. If VIN at input 109 is then suddenly lost, for example due to a condition like a power brown out condition or a power cord disconnection event, then the eFuse turns off immediately and the fault signal is asserted. The fault signal is received by the second switch SW2 102. The second switch SW2 102 responds by turning on so that power can then be supplied onto node 108 from the capacitors and/or batteries 106 in the place of the lost power. The linear voltage regulator 107 reduces the capacitor voltage down to the supply voltage “VSYS” required by the device being powered. The required system power and supply voltage VSYS can therefore be maintained for long enough to allow data that is stored in the device in volatile memory to be transferred into non-volatile storage before system power is lost altogether. This kind of prior art power loss protection system is used to power devices where high reliability is required, such as in computers like laptops and servers. If capacitors are used for block 106, then the capacitance of the capacitors must be large enough that the energy stored in the capacitors can sustain system power long enough to allow the device to complete a safe power-off sequence involving backup of configuration information and status after a loss of VIN is detected. The capacitors are sized accordingly to account for anticipated system operation and the needs of the device being powered.

SUMMARY

An integrated circuit comprises a regulator circuit, a bootstrap control circuit, and a gate driver circuit. The gate driver circuit drives a transistor pair in buck or boost mode. The transistor pair includes a high side transistor and a low side transistor. The gate driver circuit drives gates of the high side transistor and the low side transistor to switch current through an inductor in buck or boost mode. The gate driver circuit is supplied from gate driver supply voltage that is generated by the bootstrap control circuit.

The integrated circuit has a VIN terminal, STR terminal, a VOUT terminal, a HSB terminal, a SW terminal, and a PGND terminal. The VIN terminal is coupled to receive a voltage generated from an AC power source. The STR terminal is coupled to receive a voltage from a stored power source. In one example, the stored power source is a capacitor bank. The VOUT terminal is coupled to drive a load. The HSB terminal is capacitively coupled to a lead of the inductor. The SW terminal is coupled to a source of the high side transistor, to a drain of the low side transistor, and to the lead of the inductor. The PGND terminal is coupled to the source of the low side transistor.

When operating in buck mode or boost mode, the regulator circuit generates a VDD supply voltage from the stored power source. The regulator circuit supplies the generated VDD supply voltage onto the bootstrap control circuit. The bootstrap control circuit generates and supplies the gate driver supply voltage onto the gate driver supply node of the gate driver circuit. The gate driver circuit uses the received gate driver supply voltage to drive the high side and low side transistors.

When not bucking or boosting, minimal energy is drained from the stored power source. The bootstrap control circuit includes a charge pump that is coupled to the VOUT terminal. The HSB terminal is coupled to the gate driver supply node. When the gate drive circuit is not operating the high side and low side transistors in buck or boost mode, then the charge pump of the bootstrap control circuit is activated to maintain the HSB terminal within a voltage range that is greater than a voltage on the VIN terminal. The HSB terminal is maintained within the voltage range by drawing current from the VOUT terminal, which is effectively the VIN terminal when not bucking or boosting, and without drawing significant current from stored power source.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently it is appreciated that the summary is illustrative only. Still other methods, and structures and details are set forth in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.

FIG. 1 (Prior Art) is a diagram of an example of a power loss protection system.

FIG. 2A is a first part of a larger diagram of a system involving a novel power loss protection integrated circuit.

FIG. 2B is a second part of a larger diagram of a system involving a novel power loss protection integrated circuit.

FIG. 2 is a larger diagram formed by FIG. 2A and FIG. 2B.

FIG. 3 is a more detailed diagram of the current switch circuit 257 of FIG. 2.

FIG. 4 is a more detailed diagram of the health monitor circuit 259 of FIG. 2.

FIG. 5 is a more detailed diagram of one of the compare-and-mask circuits of FIG. 4.

FIG. 6 is a more detailed diagram of the input analog multiplexer circuit of FIG. 4.

FIG. 7 is a more detailed diagram of the DAC and compare circuit of FIG. 4.

FIG. 8 is a state diagram that sets forth the operation of the capacitor health monitor state machine of the capacitor health check circuit.

FIG. 9 is a table that indicates, for each 4-bit TSET[3:0] value, the corresponding time period throughout which the ten milliampere current sink is enabled.

FIG. 10 is a diagram that illustrates one capacitor health check operation as carried out by the capacitor health check circuit.

FIG. 11 is a diagram of the switching converter control circuit 261 of FIG. 2.

FIG. 12 is a more detailed diagram of the voltage reference circuit 262 of FIG. 2.

FIG. 13 is a block diagram of the I2C interface and digital register control and digital state machine circuit 258 of FIG. 2.

FIG. 14 is a circuit diagram of linear regulator (LDO) circuit 300 of FIG. 3

FIG. 15 is a flowchart of a method 320 that shows an operation of the LDO circuit 300 of FIG. 14.

FIG. 16 is a detailed circuit diagram of bootstrap control circuit 330.

FIG. 17 is a detailed circuit diagram showing how the LDO circuit 300 and bootstrap control circuit 330 operate to generate and supply gate driver supply voltage 350 onto node 351 of gate drive circuit 331.

FIG. 18 is a diagram that shows waveforms along various nodes of the integrated circuit 206.

FIG. 19 is a diagram of another embodiment of a linear regulator circuit 400.

FIG. 20 is a diagram showing operation of the linear regulator circuit 400 of FIG. 19.

DETAILED DESCRIPTION

FIG. 2A and FIG. 2B together form a larger diagram, FIG. 2.

FIG. 2 illustrates a system 201 that involves a device to be powered 202, and an AC-to-DC adapter 203. The device 202 in this particular example is a Solid State Drive (SSD) device. It includes a solid state drive system 204, a Power Management Unit (PMU) integrated circuit 205, a power loss protection integrated circuit 206, a bank of series-connected batteries 207-210, a bank of parallel-connected capacitors 211, a socket portion 212 and 213 of a connector, a DC-to-DC converter and battery charger 214, and other discrete components 215-229. The solid state drive system 204 includes, among other components not shown, a solid state memory portion 233 and a microcontroller integrated circuit 234. The AC-to-DC adapter 203 can be connected to the SSD device 202 by plugging its plug portion 230 and 231 into the socket portion 212 and 213 of the SSD device, and the AC-to-DC adapter 203 can be disconnected from the SSD device 202 by unplugging it from the socket portion. The AC-to-DC adapter 203 is coupled to receive power from a 120 volt RMS VAC 60 Hz supply voltage source 232 such as, for example, a standard residential wall socket. The SSD device 202 further includes a printed circuit board (not shown) disposed within an enclosure (not shown). The integrated circuits and other components of the SSD device 202 are mounted to the PCB and are contained in the enclosure.

Power loss protection integrated circuit 206 includes a VIN terminal 235, an EN terminal 236, a CSS terminal 237, an ISET terminal 238, several analog input terminals 239-242, a STR terminal 244, a voltage set input terminal BSET 245, a ground terminal GND 246, a CCOMP terminal 247, a VOUT terminal 263, an SCL terminal 248, a SDA terminal 249, a flag output terminal 250, a capacitor flat terminal CF 251, an HSB terminal 252, a SW terminal 253, a PGND terminal 254, an FB terminal 255, a REF terminal 256, a current switch circuit 257, an I2C interface and digital register control and digital state machine circuit 258, a health monitor circuit 259, an on-chip temperature sensor 260, a buck/boost switching converter control circuit 261, and a reference voltage circuit 262. The “terminals” mentioned above are integrated circuit terminals such as either bond pads of an integrated circuit chip or package terminals of an integrated circuit package that houses the actual integrated circuit chip.

The current switch circuit 257 is also called an eFuse circuit. The current switch circuit 257 can couple the VIN terminal 235 to the VOUT terminal 263 such that current can freely flow from the VIN terminal 235, through the current switch circuit 257, to the VOUT terminal 263, to VOUT output node 420, and to the load. When the current switch circuit 257 is ON in this way, it only introduces a 15 milliohm resistance in that current path. The current switch circuit 257 monitors the voltage on the VIN terminal. If the voltage on the VOUT terminal 263 is greater than the voltage on the VIN terminal 235, then the switch circuit 257 asserts the VOUT>VIN digital signal on conductor 286 to a digital logic high, otherwise the VOUT>VIN digital signal is a digital logic low. If the voltage on the VIN terminal is below an undervoltage value set by resistors 215 and 216, then the current switch circuit 257 is OFF such that the VIN terminal is not coupled to the VOUT terminal through the switch circuit 257. If the current switch circuit 257 detects the “UV” undervoltage condition, then it asserts the UV digital signal on conductor 264 to a digital logic high, otherwise the UV digital signal is a digital logic low. If the voltage on the VIN terminal is above a programmable overvoltage value, then the current switch circuit 257 is OFF such that the VIN terminal is not coupled to the VOUT terminal through the switch circuit 257. If the current switch 257 detects the “OV” overvoltage condition, then it asserts the OV digital signal on the OV conductor 285.

In addition to sensing voltages, the current switch circuit 257 also senses the magnitude of current flowing through the current switch between the VIN terminal and the VOUT terminal. If the current is below a predetermined high current value (A_(HC)), and if the current switch 257 is to be ON as determined by the voltage on the VIN terminal, then the current switch is fully ON (to have a resistance of 15 milliohms or less). If, however, the current is detected to reach the high current value (A_(HC)), then the current switch circuit begins to regulate the through-current so that the through-current remains at the high current value amount A_(HC) but does not exceed A_(HC). The current switch 257 does this by controlling the gate voltages on a pair of series field effect transistors through which the through-current flows. Increasing the drain-to-source resistance R_(DS) of these field effect transistors allows the flow of current to be maintained at the A_(HC) amount. If, however, the R_(DS) across the transistors becomes too high, or if the voltage on the VOUT terminal decreases too much, then the field effect transistors are not linearly regulated by controlling their R_(DS) resistances, but rather the field effect transistors are turned on and off repeatedly with a duty cycle. The duty cycle is regulated in an attempt to limit the power dropped in the current switch circuit 257. In this way, the current switch circuit 257 serves a function of limiting the magnitude of a possible large inrush current (inrush power) that might otherwise flow into the system when the SSD device is initially plugged into the AC-to-DC adapter 203 when the storage capacitors 211 are fully discharged and when the COUT capacitor 221 is fully discharged. In the present example, the inrush current limit set by the resistance of resistor RSET 218 is a current (for example, two amperes) that is larger than a typical digital logic or analog signaling input terminal or output terminal could handle.

The CSS capacitor 217 slows down the start up slew rate of the current switch circuit 257, thereby providing a “soft start” operation. The board designer can select the capacitance value of the CSS capacitor to tailor the startup slew rate as desired. If left open, the startup slew rate defaults to one millivolt per microsecond. The high current value (A_(HC)) is set by setting the resistance value of resistor RSET 218. The high current value A_(HC) is roughly equal to one volt divided by the RSET value in ohms. If the current switch circuit 257 detects the “HC” high current condition, then it asserts the HC digital signal on conductor 265 to digital logic high, otherwise the HC digital signal is a digital logic low. The current switch circuit 257 includes a current sensor/mirror circuit 290 that provides a small auxiliary current flow whose magnitude is proportional to the magnitude of the main current flow through the current switch circuit 257 from the VIN terminal to the VOUT terminal. This small mirrored auxiliary current is converted into a voltage signal by making the current flow across the RSET resistor 218. The resulting voltage signal, whose magnitude is proportional to the current flow through the switch circuit 257, is output from the current switch circuit 257 via the switch current (SC1) conductor 266. The voltage signal SC1 on the switch current SC1 conductor 266 is indicative of the magnitude of the current flowing through the current switch 257. For additional information on the structure and operation of current sense/mirror circuit 291, see U.S. patent application Ser. No. 15/476,977, now U.S. Pat. No. 10,090,675, entitled “Fast Settlement Of Supplement Converter For Power Loss Protection System,” by Lam et al. filed on Apr. 1, 2017. The entire subject matter of U.S. patent application Ser. No. 15/476,977, now U.S. Pat. No. 10,090,675, is hereby incorporated by reference.

In addition to voltage signal SC1, the current switch circuit 257 also outputs another signal (SC2). Signal SC2 is a current that is proportional to the current flowing through the current switch 257 from the VIN terminal to the VOUT terminal. This current signal SC2 is communicated via conductor 401 to the switching converter control circuit 261. In the switching converter control circuit 261, the current SC2 is converted into a voltage signal by running the current through a resistor 402.

The buck/boost switching converter control circuit 261, together with external components 220, 221 and 223-227 is operable as a buck switching converter or as a boost switching converter. When it is operating in a boost mode, the converter receives a relatively low voltage from the VOUT terminal, and outputs a boosted up relatively high voltage onto the STR terminal 244. In one example, the voltage on the VOUT terminal is 3.3 volts DC, and the voltage that the converter drives onto the STR terminal 244 is 36 volts DC. This relatively high voltage serves to charge the capacitor bank 211 capacitors up to 36 volts. The magnitude of this charging voltage is set by the value of the RBSET resistor 219. When the converter is operating in a buck mode, the converter receives a relatively high voltage from the STR terminal 244, and outputs a bucked down relatively low voltage onto the VOUT terminal 263. In one example, the voltage on the STR terminal 244 is 36 volts (as set by the RBSET resistor), and the voltage that the converter drives onto the VOUT terminal is 3.3 volts DC. The buck/boost switching converter control circuit 261 has an active high boost disable digital signal input lead BOOST_DIS1 267 and another active high boost disable digital input lead BOOST_DIS2 268. If a digital logic high signal is present on either of these inputs, then the converter is prevented (disabled) from operating in the boost mode. The buck/boost switching converter control circuit 261 also has an active high digital signal input lead BUCK ON 269. If a digital logic high signal is present on this input 269, then the converter is made to start operating in the buck mode.

The health monitor circuit 259 includes an eight-channel sigma-delta Analog-to-Digital Converter (ADC), a set of compare-and-mask circuits, and a digital state machine. The health monitor circuit 259 autonomously monitors the voltages on eight input conductors 266, and 270-276 (8 channels). If any one of these voltages is detected to be below a corresponding lower voltage limit or is detected to be above a corresponding upper voltage limit, then this undervoltage or overvoltage condition is latched into a latch of the detecting compare-and-mask circuit, and the voltage on flag terminal 250 is pulled down to ground potential. The voltage on the open-drain flag terminal 250 is otherwise not pulled down, but rather is pulled up to the VDD supply voltage by external pullup resistor 222. The low voltage (ground potential) on flag terminal 250 and conductor 277 constitutes an interrupt signal 278. This active low interrupt signal 278 is supplied via conductor 277 onto the active low interrupt input terminal 279 of microcontroller 234. The low interrupt signal therefore interrupts the microcontroller 234. The microcontroller 234 can respond to the interrupt, as further explained below, by accessing the power loss protection integrated circuit 206 via the two-wire I2C bus 280. The two conductors SDL and SDA are the two conductors of the I2C bus. The values of the lower voltage limit and the upper voltage limit for each of the eight channels is user programmable (changeable via the microcontroller 234 under software control) via the I2C interface of terminals 248 and 249. In the present example, the measurable voltage range on conductor 266 corresponds to a measured through-current flowing through the current switch 257 in the range of from zero amperes to six amperes. In the present example, the measurable voltage range on conductor 270 corresponds to a measured voltage on the VIN terminal in the range of from zero volts to twenty volts. In the present example, the measurable voltage range on conductor 271 corresponds to a measured storage capacitor voltage on the STR terminal in the range of from zero volts to thirty-six volts. In the present example, the measurable voltage range on conductor 272 corresponds to a measured on-chip temperature in the range of from minus forty degrees Celsius to plus one hundred and fifty degrees Celsius.

The health monitor circuit 259 also includes a capacitor health check circuit 299. The capacitor health check circuit 299 includes a digital state machine. If the power loss protection integrated circuit 206 is not operating in the normal mode as indicated by the active high NORMAL_MODE digital signal on conductor 288, then the capacitor health check circuit is disabled. If, however, the power loss protection integrated circuit 206 has been operating in the normal mode for a least four minutes, at the conclusion of the four minute period the state machine disables the boost converter and enables a ten milliampere current source 293. The ten milliampere current source 293 sinks current from the STR terminal 244. At the end of a time period determined by the programmable value TSET[3:0], the state machine disables the ten milliampere current source 293 and enables a fifty milliampere current source 394 that sinks current from the STR terminal 244. The fifty milliampere current source remains enabled for a period of time determined by the value TSET[3:0]. In one example, this time period is one tenth the period of time the ten milliampere current source was enabled. If at any time during the period of time when either of the two sinking current sources is enabled the voltage on the STR terminal 244 falls below a programmable voltage, then a latch 292 is set. The programmable voltage is determined by the user programmable value THR[3:0]. The setting of the latch causes the voltage on the capacitor fault terminal CF 251 to be pulled down to ground potential. This is an indication of a capacitor fault condition. This active low fault signal 353 may, for example, be supplied onto a second interrupt input terminal 287. In addition, the LED 228 is on during the time when the capacitor fault signal is asserted low.

The I2C interface and digital register control and digital state machine circuit 258 is a digital block that includes an I2C serial bus interface circuit and a digital state machine circuit. There are various digital registers disposed in various places across the integrated circuit. The digital outputs of various ones of the bits of these registers are coupled to various circuits in the integrated circuit so that the stored digital values will control and affect operation of the circuitry. Other selected bits of the registers are used to capture the digital states of corresponding nodes in the circuitry. The I2C interface is usable to read and to write to any selected one of these registers via the DATA conductors 281, the enable conductors 282, the R/W conductor 283 and the strobe conductor 284. The DATA conductors 281, the R/W conductor 283, and the strobe conductor 284 extend to all these registers. For each register, there is one dedicated enable conductor that extends from the I2C interface logic to an enable input lead of that register.

To write an 8-bit value into a particular register, the I2C interface places the data to be written onto the DATA conductors 281. Because the access is a write, the voltage on the R/W conductor 282 is driven to a digital logic low level. The enable conductors to all the registers are driven to be disabled (digital logic low), except for the one desired register that is to be written. The enable conductor to that register is driven with a digital logic high signal. After these signals are set up, the strobe signal on conductor 284 is pulsed high to clock the data into the enabled register. The 8-bit value stored in a particular register can be read by the I2C interface in similar fashion except that the I2C interface does not drive data out on the DATA conductors, but rather the I2C is setup to read in data from the DATA conductors. In addition, the digital logic value driven onto the R/W conductor is a digital logic high value. When the data bus conductors are set up this way, a pulsing of the strobe signal causes the enabled register to output its 8-bit value onto the 8-bit DATA bus, so that the 8-bit value will then be latched into the I2C interface logic. In this way, the I2C interface can read from, and can write to, any selected one of the registers on the integrated circuit.

FIG. 3 is a more detailed diagram of the current switch circuit 257 of FIG. 2.

FIG. 4 is a more detailed diagram of the health monitor circuit 259 of FIG. 2.

FIG. 5 is a more detailed diagram of one of the compare-and-mask circuits 295 of FIG. 4.

FIG. 6 is a more detailed diagram of the input analog multiplexer circuit 296 of FIG. 4.

FIG. 7 is a more detailed diagram of the DAC and compare circuit 297 of FIG. 4.

FIG. 8 is a state diagram that sets forth the operation of the capacitor health monitor state machine 298 of the capacitor health check circuit 299 of the health monitor circuit 259 of FIG. 4.

FIG. 9 is a table that indicates, for each 4-bit TSET[3:0] value, the corresponding time period throughout which the ten milliampere current sink is enabled.

FIG. 10 is a diagram that illustrates one capacitor health check operation as carried out by the capacitor health check circuit 299.

FIG. 11 is a diagram of the switching converter control circuit 261 of FIG. 2.

FIG. 12 is a more detailed diagram of the voltage reference circuit 262 of FIG. 2.

FIG. 13 is a block diagram of the I2C interface and digital register control and digital state machine circuit 258 of FIG. 2.

The magnitude of the relatively high voltage to which the converter boosts in the boost mode is user programmable, and is set by providing only one external resistor RBSET 219 of the appropriate resistance. Provided that the voltage on the voltage set input terminal BSET 245 is not below a first predetermined voltage V1 and is not above a second predetermined voltage V2, the magnitude of the resistance of this one RBSET resistor 219 corresponds directly to the magnitude of the relatively high voltage to which the STR terminal 244 is driven in the boost mode. The relatively high voltage to which the STR terminal 244 is driven in the boost mode is a gained-up version of the voltage on the BSET terminal 245. The voltage on the BSET terminal 245 is equal to the resistance of the RBSET resistor 219 multiplied by the twenty microampere current supplied by internal current source 289 of FIG. 11. Block 290 in FIG. 11 is a voltage clipping circuit. For additional information on the structure and operation of voltage clipping circuit 290, see U.S. patent application Ser. No. 15/466,681 entitled “Programmable Voltage Setting With Open And Short Circuit Protection,” by Dinh et al. filed on Mar. 22, 2017, now U.S. Pat. No. 9,946,279. The entire subject matter of U.S. patent application Ser. No. 15/466,681 is hereby incorporated by reference.

FIG. 14 is a circuit diagram of linear regulator (LDO) circuit 300 of FIG. 3. LDO circuit 300 is coupled to receive a voltage 301 from VIN terminal 235 and a voltage 302 on the STR terminal 244. LDO circuit generates and outputs VDD supply voltage 303. LDO circuit 300 comprises a first input lead 304, a second input lead 305, a first voltage regulator 306, a second voltage regulator 307, a comparator 308, an inverter 309, a multiplexer circuit 310, and an output terminal 311. LDO circuit 300 generates VDD supply voltage 303 from either voltage 301 on STR terminal 244 or voltage 302 on VIN terminal 235. VDD supply voltage 303 is generated from either STR terminal 244 or VIN terminal 235 depending on which of the voltages 312 and 313 output by regulators 306 and 307 has the higher voltage level. In one example, VT1 is 3.5 volts and VT2 is 2.8 volts.

During operation, voltage regulator 306 receives voltage signal 301 from STR terminal 244 and outputs a first regulated voltage 312. The first regulated voltage 312 is supplied to multiplexer 310. Voltage regulator 307 receives voltage signal 302 from VIN terminal 235 and outputs a second regulated voltage 313. The second regulated voltage 312 is supplied to multiplexer 310. In one example, voltage regulator 306 regulates voltage 301 to 5.0 volts, and voltage regulator 307 regulates voltage 302 to 3.6 volts.

The inverting input of comparator 308 receives the first regulated voltage 312 and the non-inverting input of comparator 308 receives the second regulated voltage 313. The output 314 of comparator 309 is supplied to inverter 309. Inverter 309 generates an inverted version of output 314 and supplies select signal 315 to multiplexer 310. The select signal 315 selects between the first regulated voltage 312 and the second regulated voltage 313. If the first regulated voltage 312 is greater than the second regulated voltage 313, then multiplexer 310 outputs the first regulated voltage 312 onto output terminal 311. If, on the other hand, the second regulated voltage 313 is greater than the first regulated voltage 312, then multiplexer 310 outputs the second regulated voltage 313 onto output terminal 311.

FIG. 15 is a flowchart of a method 320 that shows an operation of the LDO circuit 300 of FIG. 14. First (step 321), the voltage on the STR terminal 244 is compared to the voltage on the VIN terminal 235. For example, comparator 308 compares the regulated voltages 312 and 313 on the STR terminal 244 and the VIN terminal 235, respectively. If the voltage on the STR terminal 244 is greater than the voltage on the VIN terminal 235, then the VDD supply voltage 303 is generated from STR terminal 244 (step 322). If, however, the voltage on the STR terminal 244 is not greater than the voltage on the VIN terminal 235, then the VDD supply voltage 303 is generated from VIN terminal 235 (step 323).

FIG. 16 is a detailed circuit diagram of bootstrap control circuit 330. The bootstrap control circuit 330 is part of the switching converter control circuit 261 shown in FIG. 11. The bootstrap control circuit 330 supplies gate drive circuit 331 which in turn drives high side transistor Q1 332 and low side transistor Q2 333. Bootstrap control circuit 330 comprises a first input node 334, a second input node 335, a third input node 336, a fourth input node 337, a first diode 338, a charge pump 339, a second diode 340, charge pump control circuit 341, and output node 342. Bootstrap control circuit 330 generates and supplies gate driver supply voltage 350 onto gate drive circuit 331.

The charge pump control circuit 341 comprises an amplifier 342, switches 343 and 344, comparator 345, and inverter 346. The charge pump control circuit 341 receives a voltage 347 from HSB terminal 252 and voltage 348 from SW terminal 253. The charge pump control circuit 341 generates and outputs charge pump control signal CPEN 349 to charge pump 339. The charge pump control circuit 341 controls the charge pump 339 to maintain voltage 347 on HSB terminal 252 within VT1 and VT2 of SW terminal 253. In one example, VT1 is 3.5 volts and VT2 is 2.8 volts.

FIG. 17 is a detailed circuit diagram showing how the LDO circuit 300 and bootstrap control circuit 330 operate to generate and supply gate driver supply voltage 350 onto gate driver supply node 351 of gate drive circuit 331. Gate drive circuit 331, in turn, generates and supplies control signal N1 352 onto a gate of high side transistor Q1 332 and generates and supplies control signal N2 353 onto a gate of low side transistor Q2 333. Gate drive circuit 331 receives control signals HSON 334 and LSON 335 from PWM logic controller 336 shown in FIG. 11.

FIG. 18 is a diagram that shows waveforms along various nodes of the integrated circuit 206. Between time T0 and T1, integrated circuit 206 operates in startup mode. Reference numeral 340 identifies the period of time corresponding to startup mode operation. During the startup mode operation, LDO circuit 300 generates VDD supply voltage 303 from the VIN terminal 235. In startup mode operation, voltage 302 on the VIN terminal 235 is 3.0 volts whereas the voltage 301 on the STR terminal 244 is 2.5 volts. Due to the low voltages on the VIN terminal 235 and STR terminal 244, the regulators 306 and 307 of LDO circuit 300 are in dropout mode. After comparator 308 detects voltage 302 on the VIN terminal 235 (3.0 volts) is greater than voltage 301 on the STR terminal 244 (2.5 volts), multiplexer 310 selects VDD supply voltage 303 to be generated from VIN terminal 235. Between T0 and T1, the HSB terminal 252 is maintained to be between VT1 and VT2 above a voltage on SW terminal 253. The HSB terminal 252 does not draw any appreciable current from the STR terminal 244 during the startup mode.

Between time T1 and T2, integrated circuit 206 operates in boost mode 341. Reference numeral 341 identifies the period of time corresponding to boost mode operation. During boost mode operation, LDO circuit 300 generates VDD supply voltage 303 from the STR terminal 244. The gate driver supply voltage 350 is generated primarily by drawing current from capacitor bank 211.

Between time T2 and T3, integrated circuit 206 operates in suspend mode. Reference numeral 342 identifies the period of time corresponding to suspend mode operation. In suspend mode 342, integrated circuit 206 is not operating in either buck or boost mode. The VIN terminal 235 is coupled to the VOUT terminal 263 during the suspend mode. Between T2 and T3, charge pump 339 is activated and maintains the HSB terminal 252 is to be between VT1 and VT2 above a voltage on SW terminal 253. The HSB terminal 252 does not draw any appreciable current from the STR terminal 244 during the suspend mode.

Between time T3 and T4, integrated circuit 206 operates in buck mode. Reference numeral 343 identifies the period of time corresponding to buck mode operation. During buck mode operation, LDO circuit 300 generates VDD supply voltage 303 from the STR terminal 244. The gate driver supply voltage 350 is generated primarily by drawing current from capacitor bank 211.

FIG. 19 is a diagram of another embodiment of a linear regulator circuit 400. LDO circuit 400 is coupled to receive a voltage 401 from VIN terminal 235 and a voltage 402 on the STR terminal 244. LDO circuit 400 generates and outputs VDD supply voltage 403. LDO circuit 400 comprises a first input lead 404, a second input lead 405, a first voltage regulator 406, a second voltage regulator 407, a first comparator 408, a multiplexer circuit 409, a voltage divider 410, a second comparator 411, a first NOR gate 412, an AND gate 413, a second NOR gate 414, an OR gate 415, and an output terminal 416. LDO circuit 400 generates VDD supply voltage 403 in part by comparing voltage 401 on STR terminal 244 to voltage 402 on VIN terminal 235.

During operation, voltage regulator 306 receives voltage signal 401 from STR terminal 244 and outputs a first regulated voltage 417. The first regulated voltage 417 is supplied to multiplexer 409. Voltage regulator 407 receives voltage signal 402 from VIN terminal 235 and outputs a second regulated voltage 418. The second regulated voltage 318 is supplied to multiplexer 409. The inverting input of first comparator 408 receives the first regulated voltage 417 and the non-inverting input of first comparator 408 receives the second regulated voltage 418. The output of first comparator 408 is supplied to a first lead of first NOR gate 412. NOR gate 414, OR gate 415, and AND gate 413 ensure that when not operating in buck or boost mode, the VDD supply voltage is generated from VIN terminal 235. Comparator 411 and NOR gate 412 also ensure that if the voltage on the VIN terminal 235 is not above a threshold voltage TH during buck or boost operation, then the VDD supply voltage is generated from the VIN terminal 235.

FIG. 20 is a diagram showing operation of the linear regulator circuit 400 of FIG. 19. In a first step (step 451), a determination is made as to whether boost mode ore buck mode is enabled. If neither buck nor boost mode is enabled, then the VDD supply voltage is generated from the VIN terminal 235 (step 452).

If, on the other hand, buck or boost mode is enabled, then a determination is made as to whether the voltage on STR terminal 244 is greater than the voltage on VIN terminal 235 (step 453). If the voltage on STR terminal 244 is not greater than the voltage on VIN terminal 235, then the VDD supply voltage is generated from the VIN terminal 235 (step 452). If, on the other hand, the voltage on STR terminal 244 is greater than the voltage on VIN terminal 235, a determination is made as to whether the voltage on VIN terminal 235 is less than a threshold voltage TH (step 454). If the voltage on VIN terminal 235 is not less than a threshold voltage TH, then the VDD supply voltage is generated from the VIN terminal 235 (step 452). If, however, the voltage on VIN terminal 235 is less than a threshold voltage TH, then the VDD supply voltage is generated from the STR terminal 244 (step 455).

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims. 

What is claimed is:
 1. An integrated circuit comprising: a first terminal coupled to receive a first voltage generated from an alternating current (AC) power source; a second terminal coupled to receive a second voltage generated from a storage device comprising a bank of capacitors; a third terminal coupled to a load; a fourth terminal capacitively coupled to a lead of an inductor; and a gate drive circuit, wherein the gate drive circuit is configured to: drive a pair of switching transistors configured to switch current through the inductor; draw current primarily from the storage device when the pair of switching transistors are being driven; and draw current primarily from the AC power source when the pair of switching transistors are not being driven.
 2. The integrated circuit of claim 1, further comprising a bootstrap control circuit configured to maintain the fourth terminal within a maximum and minimum voltage when the pair of switching transistors are not being driven.
 3. The integrated circuit of claim 2, wherein the minimum voltage is at least half the first voltage.
 4. The integrated circuit of claim 2, further comprising a regulator circuit having a first node coupled to the first terminal, a second node coupled to the second terminal, and a third node configured to supply a VDD supply voltage.
 5. The integrated circuit of claim 4, wherein the bootstrap control circuit has a first node coupled to the third node of the regulator circuit, a second node coupled to the fourth terminal, and a third node coupled to the third terminal.
 6. The integrated circuit of claim 5, wherein the second node of the bootstrap control circuit is further coupled to supply a gate driver supply voltage for driving the pair of switching transistors to the gate drive circuit.
 7. The integrated circuit of claim 5, wherein the bootstrap control circuit comprises: a first diode having an input coupled to the first node of the bootstrap control circuit and an output coupled to the second node of the bootstrap control circuit; a charge pump circuit having an input coupled to the third node of the bootstrap control circuit; and a second diode having an input coupled to an output of the charge pump circuit, and wherein an output of the second diode is coupled to the second node of the bootstrap control circuit.
 8. The integrated circuit of claim 7, wherein the bootstrap control circuit further comprises a charge pump control circuit configured to generate and supply a charge pump control signal CPEN onto the charge pump circuit.
 9. The integrated circuit of claim 8, wherein the charge pump control signal CPEN is generated based in part on a voltage on the fourth terminal and a voltage on a fifth terminal of the integrated circuit, wherein the fifth terminal of the integrated circuit is coupled to the lead of the inductor.
 10. The integrated circuit of claim 4, wherein the regulator circuit comprises a low dropout (LDO) regulator.
 11. The integrated circuit of claim 10, wherein the LDO regulator comprises: a first voltage regulator, wherein the first voltage regulator is configured to receive the first voltage from the first terminal and output a first regulated voltage; and a second voltage regulator, wherein the second voltage regulator is configured to receive the second voltage from the second terminal and output a second regulated voltage; wherein the LDO regulator generates the VDD supply voltage based on the first regulated voltage or the second regulated voltage.
 12. The integrated circuit of claim 11, wherein the LDO regulator further comprises: a comparator having a first input lead configured to receive the first regulated voltage and a second input lead configured to receive the second regulated voltage; and a multiplexer having a first input lead coupled to receive the first regulated voltage and a second input lead coupled to receive the second regulated voltage, wherein the multiplexer outputs either the first regulated voltage or second regulated voltage based on an output of the comparator.
 13. The integrated circuit of claim 1, wherein the pair of switching transistors comprises a high side transistor and a low side transistor which are operable in a mode selected from the group consisting of: a boost operating mode, and a buck operating mode when driven by the gate drive circuit.
 14. The integrated circuit of claim 13, wherein when the high side transistor and the low side transistor are not operating in either the boost operating mode or the buck operating mode, then the integrated circuit does not draw current from the storage device.
 15. The integrated circuit of claim 13, wherein when the high side transistor and the low side transistor are not operating in either the boost operating mode or the buck operating mode, a gate driver supply voltage for the gate drive circuit is maintained between a first voltage threshold and a second voltage threshold.
 16. The integrated circuit of claim 15, wherein when the high side transistor and the low side transistor transition to operating in the buck operating mode, maintaining the gate driver supply voltage between the first voltage threshold and the second voltage threshold provides a desirable transient response. 